The RCII-SP3S400 FPGA development board is mainly for the beginners and intermediate level users that are interested in FPGA development. Therefore, the boards are designed from simplicity and practical, scalability points of views. It can also be used as prototyping for IC design.
It includes the following interfaces: DIP switch- 2 position, 8 LEDs, 4 digits 8-seg LEDs, VGA interface, USB 2.0, Serial port, SRAM, Flash, SDRAM, PS/2 keyboard and mouse, JTAG, 2X16 LCD interface and LCD display, external extentions interface.
Spartan3 XILINX XC3S400 FPGA development board FPGA evaluation boards red hurricane II generation - XILINX edition is a chip Spartan3 XILINX: based on FPGA XC3S400 40,000 LCs, equivalent to a series of 40 million door FPAG scale development board, learning board XCF02S, common configuration chip: the function, match with peripheral XILINX ISE, Platform and EDK XILINX XILINX how-to tutorials, user-friendly development FPGA.
The products feature:
1 complete Xilinx Platform development support, support MicroBlaze CPU.
USB2.0 interface, 2 480Mbps provides data transmission speed, can be used as a algorithm and high speed data acquisition boards,
3 provide interfaces for the expansion, rich, video, audio,
4 with the board of the Core provide rich design, website IP will provide the upgrade Core IP version and the latest IP Core.
5 faces the domestic and foreign customers, but independent of development-oriented customize user/or expanded plate, meet the specific application
The applicable people.
Applicable to the computer professional and electrical science class specialized undergraduate and graduate student, PhD, IC integrated circuit/IP CORE prophase design verification, the relevant scientific research institutes, such as the computer science, microelectronics, communication, measure and control technology and instrument, electrical engineering, mechanical and electrical integration, automation or related majors, Ministry, the ministry of communications, image/r &d...
[RCII - SP3S400C12 development board hardware configuration.
With 4 layer board industry standard elaborate design:
1 FPGA chip Spartan3 series XC3S400 Xilinx: LCs 40,000, equivalent to 40 million door scale.
2 configuration XCF02S: chips
3 512K high-speed, asynchronous an SRAM an uploaded file
One of the ASRAM 256K 16Bit x, independent byte enables signal
4 8M high SDARM an uploaded file
A SDRAM 16Bit x 4M, highest speed 143MHz literacy,
5 an uploaded file fast FLASH 2M
A 8Bit x x 4M 2M 16Bit Flash or reading speed for 90ns,
Flexible page mode, can be used to store the FPGA configuration files or operating system image files,
6-9 needle RS and the computer serial 232 data communications,
Auxiliary debugging, output,
7 512 color VGA interface
Direct VGA display docking, realize the show; 8 demo
For the verification VGA timing,
8 PS / 2 mouse and keyboard interface
The mouse and keyboard interface standards, support and 3.3 V, which can be used to verify 5V equipment of PS / 2
Mouth agreement and achieve a IO devices expanded,
9 USB2.0 high speed data interface
Used widely, performance and stability of Cypress CY68013A chip company realized the USB interface
With the expansion of computer, can realize the data transfer between highway,
10 LCD interface
The standard type LCD module interface, character provided 16 x2 characters of control method and the driver,
11 eight LED display
Can be used to display data during the commissioning process variables, do auxiliary debugging,
Using the buzzer in different frequency of different physical properties of the sound of the clock, through different frequency to achieve simple music,
13 four digital tube display
Used to display 4 digits,
Do auxiliary debugging, or part of the program that use the output,
14 function expansion interface
Through the corresponding expanded plate, Audio and Video, can realize network applications.
The user can also develop their definition of the interface.
The supporting software.
1 Xilinx ISE 7.1 I installation package,
2 Xilinx ChipScope Pro 7.1 I
3 I Xilinx Platform 7.1
4 I EDK 7.1 Xilinx
5 the FPGA/ASIC design resources, including textbooks, code, and more than 1GB reference design etc
The design documents.
1 development board user manual
2 development board diagram (PDF)
3 Xilinx ISE, Platform and EDK Xilinx Xilinx how-to tutorials
4 main chip data manual and simulation model (HDL language description model for system simulation),
The list of products.
1. RCII - 1 SP3S400 development board
2. Parallel cable 1 for download
3. Serial connection cable
4. USB cable
5. 1A power 1, 5V
6. Standard of 16 x2 LCD module 1
7. 1 complete DVDS
The hardware design examples of HDL.
The first chapter Xilinx ISE 7.1 I used is introduced
2 Xilinx ISE 7.1 design process
The second chapter of digital circuit experiment with digital systems
The first part of the experiment
Experiment a 3/8 decoder
Lab 2 prescaler
The second part interface control experiment
Lab 3 digital controlled experiments
Experimental four LCD display experiment
Experimental five rs-five 232 serial controller
Six VGA output control experiment experiment
Experimental 7 PS / 2 keyboard controller experiment
Experimental eight interface interconnect experiment
Buzzer control experiment. Experiment
Experimental ten infrared receiving experiment
11 table tennis game experimental demonstration experiment
In the third part of the comprehensive experimental
An SRAM test experimental twelve
13 experimental experiment
The Xilinx Platform and EDK Xilinx design examples.
The first part of the Platform and the Xilinx Xilinx EDK use 2
1 EDK Xilinx Platform and introduced Xilinx
2 EDK Xilinx Xilinx Platform and design process
The second part EDK Xilinx Platform and Xilinx experiment
Experiments LED control experiments
Lab 2 digital controlled experiments
Lab 3 serial communication experiment
The IP Core design examples.
1 color space transformation YCbCr2RGB (RIC V01) -
2 RS encoder (RIC C01) -
3 SDRAM controller (RIC M01) -
IP Core design constantly updated.
The other design examples.
1 USB2.0 interface chip and PC communications examples
2 video collection and output chip configuration examples